At last fall's Microprocessor Forum, Motorola outlined the prospective roadmap for their PowerPC line. There were two main revelations associated with this announcement: first, a new 64-bit processor, the PowerPC 7500 or G5, would be forthcoming sometime in 2001; and second the current PowerPC 7400 or G4 would be revamped to create a second generation G4 with a new microarchitecture and adjusted clock speeds to bring it more in line with the parallel speed jumps of the Intel/AMD development race.

Accompanying the second-generation G4 microarchitecture enhancements, Motorola also announced they would move production of the current G4 chips to a new silicon-on-insulator technology. Industry analysts predict that the SOI process can boost speeds by 35 percent over bulk-CMOS, or it can be used to reduce power consumption at the same speed by up to 65 percent.

The PowerPC G4-II
With the publicity the Intel/AMD clock speed race has generated, it has become harder and harder to convince the buying public that a 500MHz Apple G4 is faster than the latest 800MHz and higher processors from Intel and AMD. Savvy Mac users may know that the difference in clock speeds is due to a shorter pipeline in the G4, and that this shorter pipeline, along with a powerful backside cache configuration, contributes to the G4's ability to perform faster than the Pentium or Athlon at similar clock speeds. What they aren't sure of is whether they are getting the fastest possible G4. There is a feeling that the chip should be able to go even faster. If Intel and AMD can pump out ever higher clock speeds why can't Motorola?

To counteract this growing frustration, Motorola has come up with a slew of enhancements for the G4-II which they hope will tide Apple users over until the G5 debuts. To address the clock speed dilemma, the G4's pipeline (instruction path) has been made deeper, with 7 stages for instruction processing instead of the previous 4. These extra stages, in effect, slow the speed of instruction processing down, but they also do a better job of keeping the CPU fed with instructions and data, thus allowing for faster clock speeds.

To balance the effect of a long pipeline - a decrease in the number of instructions a processor can handle per second -- Motorola has increased the number of instruction processing units in the chip. Two additional integer units have been added for a total of four and the multimedia-boosting AltiVec system has been enhanced to handle two instructions simultaneously, with each instruction automatically passed to the appropriate unit depending on its data type.

The G4-II will use the same floating point unit, and L1 caches (32K instruction, 32K data) as the older G4, but will have an on-chip 256K L2 cache at full processor speed, connected to the L1 via a 256-bit wide datapath (up from the previous 64-bit path). It will also support up to 2MB of a third layer of backside-configured cache between the CPU and the main memory bank. The chip architecture will support up to 64GB of main memory thanks to a new 36-bit addressing mode.

Initially the chips will be manufactured with a smaller and cooler .15 micron process, but production will move to a 0.13 micron process for a chip that will run at 1.5V with a 10W power consumption. Eventually, Motorola says, the new G4 design will hit speeds of up to 1GHz. Initial G4-II systems are likely to appear in the third or fourth quarter of this year.

The 64-bit G5
Expected sometime in 2001, Motorola's PowerPC 7500 or G5 processor is likely to ship at initial speeds of around 2GHz. The G5 will be available in both 32-bit and 64-bit processor configurations. The 64-bit G5 will be capable of running 32-bit software natively, with little to no reprogramming, giving it a huge advantage over Intel's Itanium which will only run 32-bit application in emulation mode.

Also different from the Itanium, which Intel is aiming at the server and high-end workstation market, the G5 is being designed for the desktop and creative workstation market.

The G5 will feature an extensible architecture, with a new data pipeline and a new bus structure. Exact configuration details are still open to speculation. It is to be followed eventually by a G6 processor, about which even less is known. Motorola plans to offer the G3, G4, and G5 processors concurrently, with the G3 eventually moving to the growing embedded processor market.

Conclusion
It will be interesting to see what arrives on the market from Motorola and Apple between now and the third quarter of this year. Equally interesting will be seeing what Motorola presents to the industry at this year's Microprocessor Forum, in answer to the accelerated pace of chip development from AMD and Intel.