Intel's
development of the chip technology currently known as Itanium, has been
in the works for more than a decade. Initially a Hewlett-Packard design,
the EPIC (explicitly parallel instruction computing) IA-64 architecture
was brought by HP to Intel as a joint HP-Intel project in order to benefit
from Intel's higher exposure, deep market penetration, and design and
manufacturing resources.
The Itanium IA-64 chip contains an entirely new instruction set from
previous x86 and RISC chips, which it is designed to replace. The first
64-bit chip from Intel, the Itanium, as the first in a future IA-64
family (McKinley, Madison, Deerfield, Northwood, et al), is meant by
Intel to be a "unifying architecture" - used in as many high-end servers
and workstations as possible, regardless of the operating system. (See
below).
Intel and HP were the first to perceive and act on the likelihood that
new instruction sets would be needed to continue the performance increases
beyond what could be achieved with current technology. Changing instruction
sets is not a simple process to integrate into an existing market. It
is bound to cause some disruptions for end users, but this pain may
be necessary in order to gain maximum processor performance. In fact,
the path of the Intel IA-64 technology has been rocky and much slower
than originally anticipated. However, if current projections are correct,
we will see the first "Itanium Inside" systems by the third or fourth
quarter of this year.
Itanium will provide hardware emulation for IA-32/x86 instruction compatibility.
This may mean it will be much slower than Pentium chips when running
x86 instructions, and almost definitely slower than the future P7 Willamette
and Foster chips. One of Intel's goals is that software written for
desktops will run unmodified on servers and workstations as well, bridging
the current divide between these systems.
The EPIC Technology
With a 64-bit processor, a computer processes data in chunks twice
as large as those managed by the 32-bit chips found in most desktops.
64-bit chips also allow a computer to use more memory and deal with
much larger databases.
The EPIC 64-bit architecture changes how the microprocessor interacts
with applications by feeding data more effectively into the processor.
It is heavily compiler dependant, but very efficient. The focus is on
increasing instruction-level parallelism (ILP) by improving the compiler/hardware
interface, making both work more effectively in scheduling instructions.
In this way, the compiler can directly control hardware resources such
as large register files, branch predictors, the memory hierarchy, and
a number of function units, while leaving some dynamic structures in
the hardware to handle events the compiler can't easily predict. Because
the compiler has more control over branch prediction, it allows the
processor to focus only on those branches that require dynamic prediction.
The end result is a simpler more powerful chip architecture.
IA-64 processors contain huge chip execution resources to support more
registers, functional units, logic, branch predictors, instructions,
cache, and data. The Itanium contains a 10-stage instruction pipeline
to achieve high clock speeds, 128 floating point, 128 integer, 64 predict,
and 8 branch registers. Gone are the complex instruction reorder buffers
and register alias tables found in current RISC and CISC processors.
This new IA-64 technology allows the processor to achieve maximum parallelism
in high-end situations, and reduce microprocessor layout complexity
for faster processor upgrades.
Itanium fetches and executes two bundles, or six instructions, per cycle
at its peak rate, making it a six-wide machine. It is capable of 6 gigaflops,
and has 4 integer units, and 2 floating point units. It will come with
up to 4MB of L3 cache. It will feature L1 and L2 cache on-chip, while
the L3 cache will be in the Itanium package, not on-chip. OEM's will
have the option of adding L4 cache.
The Itanium is capable of dealing with up to 16GB of main memory, and
will initially ship with a new Intel 460GX chipset, using standard PC100
SDRAM at 100MHz. This chipset will come in two configurations, one for
two-processor Itanium workstations and one for four-processor servers.
Competitors
The Intel Itanium is not the only 64-bit architecture in town.
Competing processor vendors such as Compaq (Alpha), IBM (Power), AMD
(Sledgehammer), and Sun (UltraSparc) still have viable 64-bit chips
based on RISC or x86 architectures, while SGI and HP have both announced
plans to phase out their own CPU designs over the next few years in
favor of the Intel IA-64 family.
AMD's 64-bit extension to its Athlon x86 architecture - code-named SledgeHammer
-- is slated for release in 2001. Both IBM and Compaq are hedging their
bets by selling IA-64 systems as well as their own RISC systems, so
they can keep all of their customers happy. In this they face a battle
to keep their in-house RISC processors competitive with IA-64 in performance.
If they can't do so, their customers will gradually move to IA-64, reducing
the revenue available for developing faster RISC processors.
Both IBM and Compaq have unveiled their plans to keep pace with IA-64
by utilizing thread-level parallelism (TLP). IBM's Power4 will use two
actual CPUs per chip, while the Alpha EV8 will have four virtual processors
per chip. TLP is a proven method of increasing server performance by
dividing the processes up onto multiple processing threads.
The Roadmap
Intel has indicated that the Merced Itanium chip will be in production
by the middle of the year, with systems actually starting to sell around
October. Initially, processing speeds are likely to be in the 800MHz
- 1000MHz range, although prototype systems are rumored to be currently
topping at around 600MHz.
The next chip to be introduced in the IA-64 family will be the McKinley,
most likely to be called the Itanium II. This chip is supposed to double
performance because of its superior design, making many wonder why it
wasn't introduced first, instead of the Merced. It will ship with speeds
of 1GHz and up in late 2001.
Next, Intel will convert to a .13 micron process, to produce the Madison
processor, with essentially the same features as the McKinley but using
the finer manufacturing process. Madison will be the high-end IA-64
server/workstation chip succeeding McKinley probably with 4MB L2 cache
and 2003 availability.
Other Intel 64-bit chips in the works are the next-generation Celeron,
code-named Deerfield, also developed on the .13 micron process, to be
introduced by the end of 2002; and Northwood, a performance-end consumer
chip, perhaps designed to take over from the 32-bit Intel consumer line,
to be introduced in 2003 at speeds of 3GHz or more.
The Operating Systems
At this date, most of the major server and workstation OS developers
have announced IA-64-compatible versions of their software. Versions
of Unix from IBM, Santa Cruz Operation and Sequent are being rolled
into one edition code-named Monterey-64. IBM's version of Unix, called
AIX, runs only on its Power architecture chips, while both SCO and Sequent,
which IBM has recently acquired, had UNIX versions that already ran
on Intel architecture. Sequent's software also has extensions that let
its software run on servers with dozens of processors. HP's HP-UX version
of UNIX and Microsoft Windows will also be available for Itanium.
Microsoft Windows and Linux were the first two OSes that successfully
ran on the chip. IBM was next, followed by HP, with Sun (Solaris) bringing
up the rear. Compaq decided not to translate its Tru64 version of Unix
to Itanium and will instead use Monterey-64. SGI decided to use Linux,
and not its own Irix operating system with the new chip. Trillian project
members (HP, IBM, SGI, Cygnus, Red Hat, Intel, and VA Linux Systems)
are currently working to create a version of Linux for IA-64 which is
likely to meet with great success in the rapidly expanding Linux-loving
market.
