Without
question, the last 12 months have been very difficult for Intel.
Seemingly, many or most of Intel’s high-end strategies have been tainted
with disappointment – namely Rambus, Camino, MTH, Flip Chip, Profusion,
Merced and others. In these efforts, Intel has tried to undertake the
exotic, and met with frustration.
On the other hand, Intel has done well in most of its strategies for
the mainstream -- namely Celeron, the 815, etc. In these product categories,
Intel has chosen the obvious strategy and executed well. Unfortunately
for Intel, the same can be said for VIA and for AMD. While Intel overextended
itself into unrewarding strategies at the high end, AMD and VIA chose
the obvious strategies in their respective markets, and have executed
with single-mindedness. The market has responded as it always does --
in terms of design wins, OEM loyalty, and market share. Intel has been
suffering losses in all of these areas.
As such, the industry is curious to see Intel’s attitude and response
in the form of its future P3 and P4 processor roadmap with their respective
chip set platforms. The primary issues are:
-- What DRAM types will be supported on which chip sets and when?
-- What new microprocessor enhancements are in the works?
-- What enhancements are on the way for the ICH (south bridge) ?
-- How does Intel see the relative positioning of these platforms?
The Big Picture
At a high level, Intel’s latest Desktop roadmap looks something
like this:
This chart contains
lots of vital information on new processors, new MCH chips (Memory Controller
Hub, a.k.a. north bridge) and new ICH chips (I/O Controller Hub, a.k.a.
south bridge).
The diagram above will be referenced repeatedly throughout this article.
The Pentium 4 Willamette Platform
The P4 Willamette processor will be introduced later this year
in the $2000 and higher range, matched with its 850/Tehama+RDRAM platform.
Today’s ICH2 will be used. The risks associated with this platform are
known. Tehama is essentially the same as today’s 840 / AGP4x chip set
with a new front side bus interface for the P4. The Tehama MCH chip
is depicted in the photograph below, using flip chip package technology
and apparently requiring a heat sink.
Willamette is rumored
to be able to accommodate front side bus speeds of 100 and 133 MHz as
indicated in the Tehama board photograph above (first
published by the Register).
It is also rumored to be able to support 2x and 4x data rate modes for
the FSB. These combinations would enable FSB bandwidths of 1.6GB/s,
2.1, 3.2 and 4.26 GB/s. Tehama is likely to make use of the processor’s
100x4 mode exclusively, matched well to the dual channel RDRAM subsystem.
Though this extremely high bandwidth front side bus would be particularly
useful in dual processor configurations, Willamette will only work in
single processor mode. Dual processor options will be restricted to
the Foster implementation of this CPU aimed at the server market, with
large L3 caches and much higher price tags.
Primarily because of its deep, 20 stage instruction decode pipeline,
the Willamette processor is expected to deliver less than exciting performance
in mainstream applications, as compared to P3 or Athlon at a given clock
speed. Assuming identical clock speeds, the P4 is estimated to underperform
the P3 or Athlon by more than 20%.
On the flip side, the primary advantage of its 20-stage
pipeline is greater clock speed scalability. Willamette will
be able to reach higher clock speeds than the P3 in the same manufacturing
process (0.18 micron in this case). We are expecting speeds of 1.4 or
1.5GHz at launch in Q4’00, but we do not expect these systems to decisively
outperform 1.2GHz Athlons or P3s that should be available in the same
timeframe.
Since the release of Intel’s performance analysis of the 815+PC133 vs.
820+RDRAM, one might expect RDRAM to share in the blame for Willamette’s
potentially unexciting performance profile. But other factors may also
be brought to light, such as complier optimization, and more complaints
about inadequate benchmarks.
continue
to page 2:
New Northwood P4, Tualatin PIII Processors and ICH3 Chip
Intel
P4 Platform 
